Throughout my PhD I have found and reported a number of Concurrency Bugs in the Open Source GCC and LLVM compilers. A number of these have been or are being fixed by Arm’s compiler engineers. I provide a list of bugs reported here to triage and fix as appropriate.

Please note: please clear your cache if you are expecting more bugs. Page last updated 17th October 2023.

Title	Compiler	Bug Type	Architecture	Link
128-bit Const Atomic Load implemented using Store Pair instruction, induces Runtime Crash on Arm AArch64	LLVM	Runtime Crash	Armv8-a	here
128-bit seq_cst load can be reordered before prior RMW operations under LSE and above	LLVM	Concurrency Bug	Armv8-a	here
LD{AX}P/S{LX}TP endian swap	LLVM	Wrong Endian	Armv8-a	here
branch delay slots are not filled with atomic stores	GCC	Optimisation Opportunity	MIPS (64-bit)	here
Sequentially Consistent Load Allows Reordering of Prior Store when Implementations are Mixed	LLVM	Concurrency Mix Testing Bug	Armv7-a/Armv8-a	here
64-bit Sequentially Consistent Load can be Reordered before Store of RMW when v7 and v8 Implementations are Mixed	GCC	Concurrency Mix Testing Bug	Armv7-a/Armv8-a	here
Atomic Exchange Allows Reordering past Acquire Fence	LLVM	Concurrency Bug, Heisenbug	Armv8-a	here
[AArch64]: 128-bit Sequentially Consistent load allows reordering before prior store when armv8 and armv8.4 implementations are Mixed	LLVM	Concurrency Mix Testing Bug	Armv8-a/Armv8.4-a	here